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If the failing output circuits are run in a new project the RTL schematic is correct. The attached schematic screen shot shows some of the attempts to find the problem.

This schematic has no errors, but the RTL schematic doesn't connect the bidirectional io markers.

There are three important factors to determine ckt performance. Normally, if the ckt consumes more power delay is less and area is more.

NAND uses 4 transistors (CMOS logic) while NOT uses 2 transistors(CMOS logic) and AND gate uses 6 transistors(CMOS logic).

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After the HDL synthesis phase of the synthesis process, you can display a schematic representation of your synthesized source file.

This schematic shows a representation of the pre-optimized design in terms of generic symbols, such as adders, multipliers, counters, AND gates, and OR gates, that are independent of the targeted Xilinx® device.The output of memory is going as input to some other module. In the RTL schematic view am not able to see the wire connection between those two modules. Then I restarted the tool, opened project, and wanted to look at an initial RTL schematic of how the tool interpreted my code, so I clicked on "Elaborated Design." Not only did it declare my synthesis and implementation runs out of date upon starting a completely new elaboration run, but it even started new synthesis runs on all my IP, which already existed as synthesized modules.(And yes, it literally overwrote the existing modules on disk in my IP library!Using the same circuits in a new project, also schematic based and on one sheet, all of the combinations work. Both an iobuf and buft in the new project wire as expected. The failing iomarkers are on a bus and using bus names.

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